The present invention relates to semiconductor devices, and more particularly to a nonvolatile semiconductor memory device and method of fabricating the same.
Semiconductor memory devices are widely employed to store various data in electronic systems, normally classified into volatiles and nonvolatiles. Volatile memory devices lose their data when their power supply is interrupted or suspended, while the nonvolatile memory devices retain their data without power. Therefore, nonvolatile memory devices are widely used in applications such as mobile telephones, memory cards, storing audio or image files, and other portable devices in operational environments without a wired power supply.
Nonvolatile memory devices are differentiated into floating-gate types and floating-trap types. In a floating-gate memory device, a floating gate is disposed between a semiconductor substrate and a control gate, where the floating gate and substrate are separated by a tunneling insulation film. A data bit is programmed by storing an electric charge in the floating gate. The floating-trap memory device programs a data bit by storing charges in a trap, formed within a non-conductive charge storage film between a semiconductor substrate and a gate electrode.
A floating-gate memory device may lose charge due to defects in the tunneling insulation film isolating the floating gate from the semiconductor substrate. In order to remain reliable, a floating-gate memory device needs a relatively thick tunneling insulation film. A floating-trap memory device can utilize a thinner tunneling insulation film, because floating-trap memory devices have relatively low power requirements compared to the floating-gate memory devices. The relatively low power requirement, because the charges in the floating-trap memory devices are held in a trap of deep potential level.
A typical floating-trap memory structure, called a silicon-oxide-nitride-oxide-semiconductor (SONOS) cell structure, includes a channel region formed of a silicon substrate, a tunneling layer formed of a first oxide film, a charged storage film formed of a nitride film, a blocking layer formed of a second oxide film, and a control gate electrode formed of a conductive film. The charge storage film may be made of silicon nitride film or high-dielectric material film. Alternatively, the charge storage film may be formed of isolated and distributed spots such as silicon-germanium (SiGe) quantum dots, silicon quantum dots, and metallic quantum dots.
FIG. 1 is a sectional diagram of a conventional SONOS memory device, taken along the direction of bitline.
Referring to FIG. 1, the SONOS memory device has a gate stack 2 formed on a semiconductor substrate 1. The gate stack 2 includes a tunneling insulation film 3, a charge storage film 4, a blocking insulation film 5, and a conductive gate film 6 deposited in sequential layers. At both sides of the gate stack 2, source and drain regions, 7 and 8, are formed by N-type impurities.
The charge storage film 4 has a trap potential level and the SONOS memory device uses this trap potential level in operation, as follows.
Materials forming the semiconductor substrate 1, the tunneling insulation film 3, the charge storage film 4, the blocking insulation film 5, and the conductive gate film 6 are configured with different potential barriers on their surfaces. When a positive voltage is applied to the gate electrode 2 and the drain region 8 while the source region 7 is grounded, an electric field is generated along the channel leading from the source region 7 to the drain region 8. The electric field accelerates electrons from the source region 7 toward the drain region 8. A portion of the accelerated electrons overcome the potential barrier and tunnel through the tunneling insulation film 3, and are caught at the trap potential level of the charge storage film 4. As electrons are caught and accumulated at the charge storage film 4, a threshold voltage of the cell transistor increases to set the cell transistor in a programmed state (or an erased state). When a negative voltage is applied to the gate stack 3, the electrons trapped in the charge storage film 4, tunnel through the insulation film 3 and move into the semiconductor substrate 1. At the same time, holes pass through the tunneling insulation film 3 from the semiconductor substrate 1 and are caught in the charge storage film 4, resulting in a decrease of the threshold voltage which sets the cell transistor to the erased state (or the programmed state).
FIG. 2 is a sectional diagram of a conventional SONOS memory device, taken along the direction of the gate length. In FIG. 2, field isolation films 9 are formed in the semiconductor substrate 1, confining active regions therein. The field isolation films 9, the tunneling insulation film 3, the charge storage film 4, and the blocking insulation film 5, and the conductive gate film 6 are deposited in sequence on the semiconductor substrate.
As the technological trend to increase the density and reduce the size of semiconductor memory devices continues, structural design at the microscopic level, which had not posed a problem before, is becoming an increasingly critical factor in operational performance of semiconductor memory devices, such as SONOS memory devices.
FIGS. 3A and 3B illustrates problems arising from the conventional art, particularly, the problems associated with the boundary between the active regions and the field isolation films. FIG. 3A illustrates a section of a conventional SONOS memory device along the gate direction, while FIG. 3B illustrates an enlarged view of the dotted circle in FIG. 3A.
From FIG. 3A, it is evident that there are microscopic step differences between the top surface of the field isolation films 9 and the top surface of the semiconductor substrate 1 at the active region. The field isolation films 9 are generally formed, after forming a pad insulation pattern on the semiconductor substrate 1 and then forming trenches on the semiconductor substrate 1 using the pad insulation pattern as an etch mask, and filling the trenches with an insulation material. A planarization process is then carried out until the top surface of the semiconductor substrate 1 is exposed, and the pad insulation pattern is completely removed. This process inevitably causes microscopic step differences, such that the top surfaces of the field isolation films 9 are positioned minutely higher than the top surface of the active regions of the semiconductor substrate 1. As a result, as the tunneling insulation film 3, the charge storage film 4, the blocking insulation film 5, and the conductive gate film 6 are sequentially deposited in the structure having the step differences, the films 3 through 6 cannot settle in flattened profiles. As illustrated in FIG. 3A, the tunneling insulation film 3 as an example is concavely deposited on the semiconductor substrate 1 between the field isolation films 9. Previously, the step difference between the top surfaces of the field isolation films 9 and the semiconductor substrate 1 of the active regions have not been considered an important factor. However, as semiconductor devices continue to shrink in size the step difference is becoming an important factor to the operational performance of semiconductor devices.
FIG. 3B, further illustrates how the thickness of the tunneling insulation film 3 varies over the active region as a result of the step difference. When voltages are applied to the structure for programming and erasing data, an electric field varies between the center and edges of the active regions. While the electric field is uniformly formed at the center of the active region, it becomes irregular and weak near the edges of the active region where the tunneling film is thicker. The programming and erasing operations are carried out using tunneling charges accelerated by the electric field. However, the intensity of the electric field differs along the tunneling insulation film, which causes the speeds of the programming and erasing operations to be differs in the center and edges of the active region. This problem may become more serious as the memory cell sizes become smaller and the edges of the active region occupy a high percentage of the area of the cell structure.